1. Field of the Invention
The invention relates in general to a receiver, and more particularly to a receiver of data in series and signal testing method thereof.
2. Description of the Related Art
Referring to FIG. 1A a schematic diagram of a conventional loop test operation is shown. A south-bridge chip 100 with a serial advanced technology attachment (SATA) interface includes a receiver 112 and a transmitter 114. In the prior-art technology, a test signal D1 is continuously outputted from the transmitter 114 to the receiver 112 to achieve the purpose of loop testing. In the process of transmitting the test signal D1, the transmitter 114 transmits only a part of data of the test signal D1 to the receiver 112. Therefore, the clock/data recovery (CDR) circuit of the receiver 112 will follow and use the frequency of the transmitter in transmitting the test signal D1 as its own operational frequency.
Referring to FIG. 1B, a schematic diagram of an example for transmitting the test signal in FIG. 1A is shown. In order to test the correctness of the test signal D1 outputted from the transmitter 114 to the receiver 112, a conventional method is to design a number of buffers 10 in the transmitter 114. The buffers 10 are for recording patterns A1˜An of several to-be-tested signals beforehand. When the test signal D1 is transmitted from the transmitter 114 to the receiver 112, the test signal D1 is compared with the stored patterns A1˜An of the to-be-tested signals to determine whether the test signal D1 is received successfully.
In the conventional loop testing method, buffers of the receiver are used to store the patterns of the to-be-tested signals beforehand. Extra buffers are disposed in the transmitter will increase the circuit cost and power consumption in a whole in addition to increasing difficulty of circuit design. These are all drawbacks of the conventional loop testing method. Therefore, how to effectively and correctly test functions of the receiver is an essential subject in the relevant industry.